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stk14ca8 128kx8 autostore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-51592 rev. *c revised april 5, 2010 features 25 [1] , 35, 45 ns read access and read/write cycle time unlimited read/write endurance automatic nonvolatile store on power loss nonvolatile store under hardware or software control automatic recall to sram on power up unlimited recall cycles 200k store cycles 20-year nonvolatile data retention single 3.0v + 20%, -10% operation commercial and industrial temperatures small footprint soic and sso p packages (rohs compliant) description the cypress stk14ca8 is a 1 mb fast static ram with a nonvol- atile quantumtrap storage element included with each memory cell. this sram provides fast access and cycle times, ease of use, and unlimited read and wr ite endurance of a normal sram. data transfers automatically to the nonvolatile storage cells when power loss is detected (the store operation). on power up, data is automatically restored to the sram (the recall operation). both store and recall operations are also available under software control. the cypress nvsram is the first monolithic nonvolatile memory to offer unlimited writes and reads. it is the highest performing and most reliable nonvolatile memory available. row decoder input buffers column dec g e w column i/o power control hsb store/ recall control software detect a 15 ? a 0 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 quantum trap 1024 x 1024 static ram array 1024 x 1024 store recall dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 a 0 a 1 a 2 a 3 a 4 a 10 a 11 v cc v cap logic block diagram note 1. 25 ns speed in industrial temperature range is over the operating voltage range of 3.3v+ 0.3v only. [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 2 of 17 contents features............................................................................... 1 description.......................................................................... 1 logic block diagram.......................................................... 1 contents .............................................................................. 2 pinouts ................................................................................ 3 pin descriptions ................................................................. 3 absolute maximum ratings .............................................. 4 dc characteristics ............................................................. 4 capacitance ........................................................................ 6 sram read cycles #1 and #2 .................................... 7 sram write cycles #1 and #2................................... 8 autostore/power up recall ........................................ 9 software controlled store/recall cycle .................. 10 hardware store cycle ................................................... 11 soft sequence commands ............................................... 11 mode selection ................................................................. 12 nvsram operation........................................................... 13 nvsram ...................................................................... 13 sram read ............................................................... 13 sram write ............................................................. 13 autostore operation.................................................... 13 hardware store (hsb) operat ion............................ 13 hardware recall (power up) ................................... 13 software store......................................................... 14 software recall ....................................................... 14 data protection............................................................ 14 noise considerations .................................................. 14 best practices ............................................................. 14 low average active power ......................................... 15 preventing autostore....................................................... 15 package diagrams............................................................ 17 document history page .................................................... 18 sales, solutions, and legal information ........................ 18 worldwide sales and design supp ort............. ............ 18 products ...................................................................... 18 [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 3 of 17 pinouts figure 1. 48-pin ssop figure 2. 32-pin soic figure 3. relative pcb area usage [2] pin descriptions v ss a 14 a 12 a 7 a 6 dq 0 dq 1 v cc dq 2 a 3 a 2 a 1 v cap a 13 a 8 a 9 a 11 a 10 dq 7 dq 6 v ss a 0 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc nc 23 24 a 5 nc nc nc nc nc nc a 4 48 47 46 45 v cc hsb nc nc w nc nc dq 5 dq 3 dq 4 g e a 16 a 15 note 2. see package diagrams on page 16 for detailed package size specifications. a 16 a 14 a 12 a 7 dq 0 dq 1 dq 2 a 4 a 2 a 1 v cap a 13 a 8 a 9 a 11 a 10 dq 7 dq 6 v ss a 0 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 6 a 3 a 5 32 31 30 29 v cc hsb w dq 5 dq 3 dq 4 g e a 15 pin name i/o description a 16 -a 0 input address: the 17 address inputs select one of 131,072 bytes in the nvsram array. dq 7 -dq 0 i/o data: bi-directional 8-bit data bus for accessing the nvsram. e input chip enable: the active low e input selects the device. w input write enable: the active low w allows to write the data on the dq pins to the address location latched by the falling edge of e. g input output enable: the active low g input enables the data outp ut buffers during read cycles. de-asserting g high causes the dq pins to tri-state. v cc power supply power: 3.0v, +20%, -10%. hsb i/o hardware store busy : when low this output indicates a store is in progress. when pulled low external to the chip, it initiates a nonvolatile store operation. a weak pull up resistor keeps this pin high if not connected. (connection is optional). v cap power supply autostore capacitor: supplies power to nvsram during power loss to store data from sram to nonvolatile storage elements. v ss power supply ground. nc no connect unlabeled pins have no internal connections. [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 4 of 17 absolute maximum ratings voltage on input relative to ground.................?0.5v to 4.1v voltage on input relative to v ss ...........?0.5v to (v cc + 0.5v) voltage on dq 0-7 or hsb ......................?0.5v to (v cc + 0.5v) temperature under bias ............................... ?55 c to 125 c junction temperature ................................... ?55 c to 140 c storage temperature .................................... ?65 c to 150 c power dissipation...................... ....................................... 1w dc output current (1 output at a time, 1s duration).... 15 ma nf (sop-32) package thermal characteristics jc 5.4 c/w; ja 44.3 [0fpm], 37.9 [200f pm], 35.1 c/w [500fpm]. rf (ssop-48) package thermal characteristics jc 6.2 c/w; ja 51.1 [0fpm], 44.7 [200f pm], 41.8 c/w [500fpm]. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at conditions above those indi cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc characteristics (v cc = 2.7v to 3.6v) note the hsb pin has i out =-10 ua for v oh of 2.4 v, this parameter is characterized but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 average v cc current 65 55 50 70 60 55 ma ma ma t avav = 25 ns t avav = 35 ns t avav = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i cc 2 average v cc current during store 3 3 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ) i cc 3 average v cc current at t avav = 200 ns 3v, 25c, typical 10 10 ma w (v cc ? 0.2v) all other inputs cycling at cmos levels dependent on output loading and cycle rate. values obtained without output loads. i cc 4 average v cap current during autostore cycle 3 3 ma all inputs don?t care average current for duration of store cycle (t store ) i sb v cc standby current (standby, stable cmos levels) 33 m a e ( v cc -0.2v) all others v in 0.2v or (v cc -0.2v) standby current level after nonvolatile cycle complete i ilk input leakage current 1 1 av cc = max v in = v ss to v cc i olk off-state output leakage current 1 1 av cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.0 v cc +0.3 2.0 v cc +0.3 v all inputs v il input logic ?0? voltage v ss ?0.5 0.8 v ss ?0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 2 ma v ol output logic ?0? voltage 0.4 0.4 v i out = 4 ma t a operating temperature 0 70 ?40 85 c v cc operating voltage 2.7 3.6 2.7 3.6 v 3.0v +20%, -10% v cap storage capacitance 17 120 17 120 fbetween v cap pin and v ss , 5v rated. nv c nonvolatile store operations 200 200 k data r data retention 20 20 years at 55 c [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 5 of 17 ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times ................................................. 5 ns input and output timing reference levels .................... 1.5v output load.............. .............. ......see figure 4 and figure 5 capacitance (t a = 25 c, f = 1.0 mhz) figure 4. ac output loading figure 5. ac output loading for tristate specifications (t hz , t lz , t wlqz , t whqz , t glqx , t ghqz ) symbol parameter [3] max units conditions c in input capacitance 7 pf v = 0 to 3v c out output capacitance 7 pf v = 0 to 3v 577 ohms 30 pf 789 ohms 3.0v including scope and output fixture 577 ohms 5 pf 789 ohms 3.0v including scope and output fixture note 3. these parameters are guaranteed but not tested. [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 6 of 17 sram read cycles #1 and #2 figure 6. sram read cy cle #1: address controlled [4, 5, 7] figure 7. sram read cycle #2: e and g controlled [4, 7] no. symbols parameter stk14ca8-25 [1] stk14ca8-35 stk14ca8-45 units #1 #2 alt. min max min max min max 1 t elqv t acs chip enable access time 25 35 45 ns 2 t avav [4] t eleh [4] t rc read cycle time 25 35 45 ns 3 t avqv [5] t avqv [5] t aa address access time 25 35 45 ns 4 t glqv t oe output enable to data valid 12 15 20 ns 5 t axqx [5] t axqx [5] t oh output hold after address change 333ns 6 t elqx t lz address change or chip enable to output active 333ns 7 t ehqz [6] t hz address change or chip disable to output inactive 10 13 15 ns 8 t glqx t olz output enable to output active 0 0 0 ns 9 t ghqz [6] t ohz output disable to output inactive 10 13 15 ns 10 t elicch [3] t pa chip enable to power active 0 0 0 ns 11 t ehiccl [3] t ps chip disable to power standby 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav notes 4. w must be high during sram read cycles. 5. device is continuously selected with e and g both low 6. measured 200mv from steady state output voltage. 7. hsb must remain high during read and write cycles 2 29 11 7 9 10 8 4 3 6 1 [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 7 of 17 sram write cycles #1 and #2 figure 8. sram write cycle #1: w controlled [8,9] figure 9. sram write cycle #2: e controlled [8,9] no. symbols parameter stk14ca8-25 [1] stk14ca8-35 stk14ca8-45 units #1 #2 alt. min max min max min max 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data setup to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address setup to end of write 20 25 30 ns 18 t avwl t avel t as address setup to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz [6,8] t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 3 3 3 ns notes 8. if w is low when e goes low, the outputs remain in the high impedance state. 9. e or w must be v ih during address transitions. previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data in 12 t avav 16 t ehdx 13 t wleh 19 t ehax 18 t avel 17 t aveh data valid 15 t dveh high impedance 14 t eleh data out e address w data in [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 8 of 17 autostore/power up recall t figure 10. autostore/power up recall note read and write cycles are ignored during store, recall, and while v cc is below v switch. no. symbols parameter stk14ca8 units notes standard alternate min max 22 t hrecall power up recall duration 20 ms 10 23 t store t hlhz store cycle duration 12.5 ms 11, 12 24 v switch low voltage trigger level 2.65 v 25 v ccrise v cc rise time 150 s notes 10. t hrecall starts from the time v cc rises above v switch 11. if an sram write has not tak en place since the last nonvolatile cycle, no store takes place 12. industrial grade devices require maximum 15 ms. 25 23 23 22 22 [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 9 of 17 software controlled store/recall cycle figure 11. software store/recall cycle: e controlled [14] figure 12. software store/recall cycle: g controlled [14] no. symbols parameter [13,14] stk14ca8-25 [1] stk14ca8-35 stk14ca8-45 units notes e cont g cont alt min max min max min max 26 t avav t avav t rc store/recall initiation cycle time 25 35 45 ns 14 27 t avel t avgl t as address setup time 0 0 0 ns 28 t eleh t glgh t cw clock pulse width 20 25 30 ns 29 t ehax t ghax address hold time 1 1 1 ns 30 t recall t recall recall duration 50 50 50 s 26 26 27 28 29 23 30 26 26 27 28 29 23 30 notes 13. the software sequence is clocked on the falling edge of e controlled reads or g controlled reads 14. the six consecutive addresses must be read in the order listed in the software store/recall mode selection table. w must be high during al l six consecutive cycles. [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 10 of 17 hardware store cycle figure 13. hardware store cycle soft sequence commands figure 14. software sequence commands no. symbols parameter stk14ca8 units notes standard alternate min max 31 t delay t hlqz hardware store to sram disabled 1 70 s 15 32 t hlhx hardware store pulse width 15 ns 32 23 31 no. symbols parameter stk14ca8 units notes standard min max 33 t ss soft sequence processing time 70 s16, 17 33 33 notes 15. on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read/write cycles to complete. 16. this is the amount of time that it takes to take action on a soft sequence command. vcc power must remain high to effectivel y register command. 17. commands such as store and recall lock out i/o until operation is complete which further increases this time. see specific c ommand. [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 11 of 17 mode selection e w g a 16 -a 0 mode i/o power notes h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x08b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active 18, 19, 20 l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active 18, 19, 20 l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f read sram read sram read sram read sram read sram output data output data output data output data output data active 18, 19, 20 0x08fc0 nonvolatile store output high z i cc2 l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active 18, 19, 20 notes 18. the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. 19. while there are 17 addresses on the stk14ca8, only the lower 16 are used to control software modes 20. i/o state depends on the state of g . the i/o table shown assumes g low [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 12 of 17 nvsram operation nvsram the stk14ca8 nvsram has two functional components paired in the same physical cell. these are the sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates similar to a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the stk14ca8 supports unlimited read and writes similar to a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 200k store operations. sram read the stk14ca8 performs a read cycle whenever e and g are low while w and hsb are high. the address specified on pins a 0-16 determine which of the 131,072 data bytes are accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t avqv (read cycle #1). if the read is initiated by e and g , the outputs are valid at t elqv or at t glqv , whichever is later (read cycle #2) . the data outpu ts repeatedly responds to address changes within the t avqv access time without the need for transitions on any control input pins, and remains valid until another address change or until e or g is brought high, or w and hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq0-7 are written into me mory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write. it is recommended that g be kept high during the entire write cycle to avoid data bus contenti on on common i /o lines. if g is left low, internal circuitry turns off the output buffers t wlqz after w goes low. autostore operation the stk14ca8 stores data to nvsram using one of three storage operations. these three op erations are hardware store (activated by hsb), software store (activated by an address sequence), and autostore (on power down). autostore operation is a uniq ue feature of cypress quantum trap technology is enabled by default on the stk14ca8. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 15 shows the proper connection of the storage capacitor (v cap ) for automati c store operation. refer to dc characteristics on page 4 for the size of the capacitor. the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up should be placed on w to hold it inactive during power up. to reduce unneeded nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore cycle is in progress. figure 15. autostore mode hardware store (hsb ) operation the stk14ca8 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the stk14ca8 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram took place since the last store or recall cycle. the hsb pin has a very resistive pull up and is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. this pin should be externally pulled up if it is used to drive other inputs. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk14ca8 continues to allow sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low, it is allowed a time t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. if hsb is not used, it should be left unconnected. hardware recall (power up) during power up or after any low power condition (v cc stk14ca8 document number: 001-51592 rev. *c page 13 of 17 software store data can be transferred from the sram to the nonvolatile memory by a software address sequence. the stk14ca8 software store cycle is initia ted by executin g sequential e controlled or g controlled read cycles from six specific address locations in exact order. during the store cycle, previous data is erased and then the new data is programmed into the nonvol- atile elements. after a store cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. to initiate the software store cycle, the following read sequence must be performed: when the sixth address in the se quence is entered, the store cycle commences and the chip is disabled. it is important that read cycles and not write cycles be used in the sequence and that g is active. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data can be transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of e controlled or g controlled read operations must be performed: internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is trans- ferred into the sram cells. after the t recall cycle time, the sram is again ready for read or write operations. the recall operation in no way alters the data in the nonvolatile storage elements. data protection the stk14ca8 protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc stk14ca8 document number: 001-51592 rev. *c page 14 of 17 low average active power cmos technology provides the stk14ca8 with the benefit of power supply current that scale s with cycle time. less current is drawn as the memory cycle time becomes longer than 50 ns. figure 16 shows the relationship between i cc and read/write cycle time. worst case current consumption is shown for commercial temperature range, v cc =3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the stk14ca8 depends on the following items: 1. the duty cycle of chip enable 2. the overall cycle rate for operations 3. the ratio of reads to writes 4. the operating temperature 5. the vcc level 6. i/o loading figure 16. current vs cycle time preventing autostore the autostore function can be disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initi- ation. to initiate the autostore disable sequence, the following sequence of e controlled or g controlled read operations must be performed: the autostore can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of e controlled or g controlled read operations must be performed: if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with au tostore enabled. read address 0x4e38 valid read read address 0xb1c7 valid read read address 0x83e0 valid read read address 0x7c1f valid read read address 0x703f valid read read address 0x8b45 autostore disable read address 0x4e38 valid read read address 0xb1c7 valid read read address 0x83e0 valid read read address 0x7c1f valid read read address 0x703f valid read read address 0x4b46 autostore enable [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 15 of 17 ordering information ordering codes these parts are not recommended for new designs. packing option blank=tube tr=tape and reel temperature range blank=commercial (0 to +70 c) i= industrial (-45 to +85 c) access time 25=25 ns 35=35 ns 45=45 ns lead finish f=100% sn (matte tin) rohs compliant package n=plastic 32-pin 300 mil soic (50 mil pitch) r=plastic 48-pin 300 mil ssop (25 mil pitch) stk14ca8-r f 45 itr part number description access times temperature stk14ca8-nf25 3v 128kx8 autostore nvsram sop32-300 25 ns commercial stk14ca8-nf35 3v 128kx8 autostore nvsram sop32-300 35 ns commercial stk14ca8-nf45 3v 128kx8 autostore nvsram sop32-300 45 ns commercial stk14ca8-nf25tr 3v 128kx8 autostore nvsram sop32-300 25 ns commercial stk14ca8-nf35tr 3v 128kx8 autostore nvsram sop32-300 35 ns commercial stk14ca8-nf45tr 3v 128kx8 autostore nvsram sop32-300 45 ns commercial stk14ca8-rf25 3v 128kx8 autostore nvsram ssop48-300 25 ns commercial stk14ca8-rf35 3v 128kx8 autostore nvsram ssop48-300 35 ns commercial stk14ca8-rf45 3v 128kx8 autostore nvsram ssop48-300 45 ns commercial stk14ca8-rf25tr 3v 128kx8 autostore nvsram ssop48-300 25 ns commercial stk14ca8-rf35tr 3v 128kx8 autostore nvsram ssop48-300 35 ns commercial stk14ca8-rf45tr 3v 128kx8 autostore nvsram ssop48-300 45 ns commercial stk14ca8-nf25i 3.3v 128kx8 autostore nvsram sop32-300 25 ns industrial stk14ca8-nf35i 3v 128kx8 autostore nvsram sop32-300 35 ns industrial stk14ca8-nf45i 3v 128kx8 autostore nvsram sop32-300 45 ns industrial STK14CA8-NF25ITR 3.3v 128kx8 autostore nvsram sop32-300 25 ns industrial stk14ca8-nf35itr 3v 128kx8 autostor e nvsram sop32-300 35 ns industrial stk14ca8-nf45itr 3v 128kx8 autostor e nvsram sop32-300 45 ns industrial stk14ca8-rf25i 3.3v 128kx8 autostore nvsram ssop48-300 25 ns industrial stk14ca8-rf35i 3v 128kx8 autostore nvsram ssop48-300 35 ns industrial stk14ca8-rf45i 3v 128kx8 autostore nvsram ssop48-300 45 ns industrial stk14ca8-rf25itr 3.3v 128kx8 autostore nvsram ssop48-300 25 ns industrial stk14ca8-rf35itr 3v 128kx8 autostor e nvsram ssop48-300 35 ns industrial stk14ca8-rf45itr 3v 128kx8 autostor e nvsram ssop48-300 45 ns industrial [+] feedback not recommended for new designs
stk14ca8 document number: 001-51592 rev. *c page 16 of 17 package diagrams figure 17. 32-pin 300 mil soic (51-85127) figure 18. 48-pin 300 mil ssop (51-85061) pin 1 id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 51-85127 *b 51-85061 *d [+] feedback not recommended for new designs
document number: 001-51592 rev. *c revised april 5, 2010 page 17 of 17 all other products and company names mentioned in this document may be the trademarks of their respective holders. stk14ca8 ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: stk14ca8 128kx8 autostore nvsram document number: 001-51592 revision ecn orig. of change submission date description of change ** 2665610 gvch/pyrs 02/04/09 new data sheet *a 2821358 gvch 12/04/09 added note in ordering info rmation mentioning that these parts are not recommended for new designs. added ?not recommended for new designs? watermark in the pdf. added contents on page 2. *b 2895330 gvch 03/18/10 added foot note 1 for 25ns access speed, updated package diagram 48-pin 300 mil ssop. updated ordering codes description *c 2902517 gvch 03/31/2010 added watermark "not recommended for new designs" in pdf version. move to external web. [+] feedback not recommended for new designs

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